2026/04 Newsletter
In the competitive landscape of advanced semiconductor packaging (such as CoWoS and large-scale AI chips), the quality of dies after singulation is a critical determinant of final yield. Many failures do not occur at the moment of dicing but remain latent as "delayed destruction" within the process details. This technical newsletter systematically analyzes the root causes of these failures across three dimensions: physical mechanisms, material properties, and process parameters.
1. Core Physical Mechanism: Formation and Propagation of Micro-cracks:
Silicon cracking is essentially a process of energy release. It is crucial to distinguish between two distinct stages: "Damage Implantation" and "Stress Triggering."
- Subsurface Damage (SSD):
During the blade dicing process, mechanical force and high-frequency vibrations generate micro-cracks at the die edges that are invisible to the naked eye. The depth of this SSD increases significantly when blade conditions are poor (e.g., worn or incorrect grit), feed rates are too fast, or spindle speeds are not optimized. - Crack Propagation:
After singulation, the die loses the structural support of the neighboring material. The latent SSD at the edges begins to expand under subsequent environmental stress due to Stress Concentration, eventually evolving into visible edge chipping or full-thickness cracks.
2. Analysis of Key Stress Sources:
- Coefficient of Thermal Expansion (CTE) Mismatch：
This is the primary driver of delayed cracking. There is a vast disparity between the thermophysical properties of blue tape (PVC/PO) and silicon:
Silicon (Si): CTE is extremely low, approximately 2.6 ppm/°C.
Blue Tape: Highly elastic and thermosensitive, with a CTE ranging from 50–200 ppm/°C.
During UV curing, ambient temperature fluctuations, or storage, the tape expands or contracts far more than the silicon, generating intense tensile stress at the die edges. - Tape Adhesion and Peel Stress：
While the tape holds the dies in place after dicing, the edges are subjected to severe Peel force during subsequent tape expansion or Pick-up. If the adhesion is too strong due to incomplete UV curing, thin dies are highly susceptible to mechanical damage at this stage. - Wafer Thinning and Residual Backside Stress：
As advanced packaging like CoWoS thins wafers to below 100µm, the structural strength of the silicon drops exponentially. If residual stress from Back grinding is not thoroughly eliminated via CMP (Chemical Mechanical Polishing), it creates a cumulative effect with dicing damage, making the die hypersensitive to even minor stresses.
3. Failure Locations and Geometric Effects:
Empirical data shows that failures are typically concentrated in the following high-risk areas:
Die Corners: Geometric points of stress concentration and the areas most severely affected by tape tugging.
- Large Dies:
Due to the increased surface area, these chips experience higher levels of cumulative Warpage stress. - Functional Edges:
Areas near TSV (Through-Silicon Via) or interposer edges, where structural discontinuities facilitate crack propagation.
4.Process Failure Risks and Technical Solutions Table:
| Process Stage | Failure Risk Indicator | Root Cause | Technical Solutions |
|---|---|---|---|
| Wafer Dicing | Subsurface Damage (SSD) | Blade wear, non-optimized parameters | Monitor blade life; precisely calibrate feed rate and spindle speed. |
| Back grinding | Residual stress accumulation | Blade wear, non-optimized parameters | Implement CMP stress relief to enhance fracture strength. |
| Tape & Frame | Thermal mismatch tensile stress | Excessive CTE disparity; ambient temperature variance | Use low-shrinkage tape; strictly control storage temperature and humidity. |
| Tape & Frame | Thermal mismatch tensile stress | Excessive CTE disparity; ambient temperature variance | Use low-shrinkage tape; strictly control storage temperature and humidity. |
| Die Pick-up | Peel and extrusion damage | Excessive adhesion; high ejector pin force | Optimize UV curing dosage; adjust pick-up ejector pin parameters. |
5. Engineering Recommendations and Inspection Technology:
- Inspection Technology Innovation:
Traditional AOI can only identify surface defects. For advanced packaging, Infrared (IR) Inspection should be implemented. Leveraging the IR-transparency of silicon, IR tools can effectively identify internal cracks hidden beneath the blue tape that have not yet reached the surface. - Preventative Quality Control:
Silicon fracturing after singulation is the result of "cumulative damage." Engineers should treat "controlling initial dicing micro-cracks" and "reducing subsequent thermal/mechanical stress" as equally vital tasks, rather than investigating failures as isolated incidents.
6.Conclusion:
Understanding the dynamic stress interactions between dicing tape and the process environment enables engineers to proactively eliminate potential failure factors during both design and manufacturing stages. Maintaining high yield fundamentally relies on a deep understanding of microscopic physical mechanisms as well as macroscopic material stress.
In summary, edge chipping and cracking silicon dies after singulation are essentially the result of cumulative effects from initial damage and subsequent stress loading. The ability to identify defects before they evolve into visible failures is critical for effective risk control and yield improvement in advanced packaging processes. Therefore, integrating process optimization with appropriate inspection technologies, and establishing a comprehensive management framework from damage initiation to defect detection, has become an essential direction for the industry.
Scientech Corporation continues to strengthen its capabilities in both process and inspection technologies through group-level resource integration, aiming to provide more comprehensive solutions for quality and reliability enhancement.
For further insights into inspection technologies and related applications, readers are encouraged to explore Scientech’s previously published technical articles on non-destructive inspection and advanced packaging diagnostics.
